Motoyoshi, M. et al. Through-silicon via (TSV). Proc. IEEE 97, 43–48 (2009).
Google Scholar
Shen, W.-W. & Chen, K.-N. Three-dimensional integrated circuit (3D IC) key technology: through-silicon via (TSV). Nanoscale Res. Lett. 12, 1–9 (2017).
Google Scholar
Wong, S. et al. Monolithic 3D integrated circuits. In Proc. 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 1–4 (IEEE, 2007).
Topol, A. W. et al. Three-dimensional integrated circuits. IBM J. Res. Dev. 50, 491–506 (2006).
Google Scholar
Patti, R. S. Three-dimensional integrated circuits and the future of system-on-chip designs. Proc. IEEE 94, 1214–1224 (2006).
Google Scholar
Shulaker, M. M. et al. Three-dimensional integration of nanotechnologies for computing and data storage on a single chip. Nature 547, 74–78 (2017).
Google Scholar
Wolf, W., Jerraya, A. A. & Grant, M. Multiprocessor system-on-chip (MPSoC) technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27, 1701–1713 (2008).
Google Scholar
Vinet, M. et al. Opportunities brought by sequential 3D CoolCubeTM integration. In Proc. 2016 46th European Solid-State Device Research Conference (ESSDERC) 226–229 (IEEE, 2016).
Clermidy, F., Billoint, O., Sarhan, H. & Thuries, S. Technology scaling: the CoolCubeTM paradigm. In Proc. 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) 1–4 (IEEE, 2015).
Park, J.-H., et al. Low temperature (≤ 380°C) and high performance Ge CMOS technology with novel source/drain by metal-induced dopants activation and high-k/metal gate stack for monolithic 3D integration. In Proc. 2008 IEEE International Electron Devices Meeting 1–4 (IEEE, 2008).
En, W. G. et al. The Genesis Process/sup TM: a new SOI wafer fabrication method. In Proc. 1998 IEEE International SOI Conference (Cat No. 98CH36199) 163–164 (IEEE, 1998).
Kim, M. et al. Fabrication of Ge-on-insulator wafers by Smart-CutTM with thermal management for undamaged donor Ge wafers. Semicond. Sci. Technol. 33, 015017 (2017).
Google Scholar
Kim, K. S. et al. Non-epitaxial single-crystal 2D material growth by geometric confinement. Nature 614, 88–94 (2023).
Google Scholar
Liu, Y. et al. Promises and prospects of two-dimensional transistors. Nature 591, 43–53 (2021).
Google Scholar
Zhou, J. et al. A library of atomically thin metal chalcogenides. Nature 556, 355–359 (2018).
Google Scholar
Zhu, J. et al. Low-thermal-budget synthesis of monolayer molybdenum disulfide for silicon back-end-of-line integration on a 200 mm platform. Nat. Nanotechnol. 18, 456–463 (2023).
Google Scholar
Hoang, A. T. et al. Low-temperature growth of MoS2 on polymer and thin glass substrates for flexible electronics. Nat. Nanotechnol. 18, 1439–1447 (2023).
Google Scholar
Qin, B. et al. General low-temperature growth of two-dimensional nanosheets from layered and nonlayered materials. Nat. Commun. 14, 304 (2023).
Google Scholar
Yeh, C.-H., Cao, W., Pal, A., Parto, K. & Banerjee, K. Area-selective-CVD technology enabled top-gated and scalable 2D-heterojunction transistors with dynamically tunable Schottky barrier. In Proc. 2019 IEEE International Electron Devices Meeting (IEDM) (IEEE, 2019).
Yeh, C.-H. et al. Ultrafast monolayer In/Gr-WS2-Gr hybrid photodetectors with high gain. ACS Nano 13, 3269–3279 (2019).
Google Scholar
Guimaraes, M. H. D. et al. Atomically thin ohmic edge contacts between two-dimensional materials. ACS Nano 10, 6392–6399 (2016).
Google Scholar
Ryckaert, J., et al. The Complementary FET (CFET) for CMOS scaling beyond N3. In Proc. 2018 IEEE Symposium on VLSI Technology 141–142 (IEEE, 2018).
Kang, J.-H. et al. Monolithic 3D integration of 2D materials-based electronics towards ultimate edge computing solutions. Nat. Mater. 22, 1470–1477 (2023).
Google Scholar
Porter, D. A., Easterling, K. E. & Sherif, M. Y. in Phase Transformations in Metals and Alloys 382–440 (CRC Press, 1992).
Zhang, Y. et al. Controlled growth of high-quality monolayer WS2 layers on sapphire and imaging its grain boundary. ACS Nano 7, 8963–8971 (2013).
Google Scholar
Li, W. et al. Approaching the quantum limit in two-dimensional semiconductor contacts. Nature 613, 274–279 (2023).
Google Scholar
Shen, P.-C. et al. Ultralow contact resistance between semimetal and monolayer semiconductors. Nature 593, 211–217 (2021).
Google Scholar
Kozhakhmetov, A. et al. Scalable BEOL compatible 2D tungsten diselenide. 2D Mater. 7, 015029 (2019).
Google Scholar
Hwangbo, S., Hu, L., Hoang, A. T., Choi, J. Y. & Ahn, J.-H. Wafer-scale monolithic integration of full-colour micro-LED display using MoS2 transistor. Nat. Nanotechnol. 17, 500–506 (2022).
Google Scholar
Givargizov, E. I. Oriented Crystallization on Amorphous Substrates (Springer, 2013).
Wang, Y. et al. P-type electrical contacts for 2D transition-metal dichalcogenides. Nature 610, 61–66 (2022).
Google Scholar
Kim, K. S. et al. The future of two-dimensional semiconductors beyond Moore’s law. Nat. Nanotechnol 19, 895–906 (2024).
Google Scholar
Samavedam, S. B. et al. Future logic scaling: Towards atomic channels and deconstructed chips. In Proc. 2020 IEEE International Electron Devices Meeting (IEDM) 1.1.1–1.1.10 (IEEE, 2020).
IRDS. International Roadmap for Devices and Systems (IRDS™) 2022 Edition: Executive Summary (IEEE, 2022).
Ahmed, Z., et al. Introducing 2D-FETs in device scaling roadmap using DTCO. In Proc. 2020 IEEE International Electron Devices Meeting (IEDM) 22–25 (IEEE, 2020).
Kresse, G. & Jürgen, F. Efficiency of ab-initio total energy calculations for metals and semiconductors using a plane-wave basis set. Comput. Mater. Sci. 6, 15–50 (1996).
Google Scholar
Kresse, G. & Jürgen, F. Efficient iterative schemes for ab initio total-energy calculations using a plane-wave basis set. Phys. Rev. B 54, 11169–11186 (1996).
Google Scholar
Grimme, S., Antony, J., Ehrlich, S. & Krieg, H. A consistent and accurate ab initio parametrization of density functional dispersion correction (DFT-D) for the 94 elements H-Pu. J. Chem. Phys. 132, 154104 (2010).
Google Scholar
Mignuzzi, S. et al. Effect of disorder on Raman scattering of single-layer MoS2. Phys. Rev. B 91, 195411 (2015).
Google Scholar
Liang, J. et al. Impact of post-lithography polymer residue on the electrical characteristics of MoS2 and WSe2 field effect transistors. Adv. Mater. Interfaces 6, 1801321 (2019).
Google Scholar
